1. Field of the Invention
The present invention relates to a radiation detecting apparatus for detecting a radiation such as an X-ray or a γ-ray, in particular, a radiation detecting apparatus applied to a medical imaging diagnostic apparatus, a nondestructive testing apparatus, an analyzer using the radiation, or the like and to a manufacturing method therefor.
2. Related Background Art
Up to now, a photographing method adopted in the field of medical imaging diagnosis has been generally classified into ordinary photographing for obtaining a still image and fluorography for obtaining a moving image. The respective photographing methods are selected while taking into consideration a photographing apparatus as needed.
In recent years, along with progress in liquid crystal TFT technology and improvement in information infrastructure construction, a flat panel detector (hereinafter, abbreviated to FPD) has been proposed, which includes: a sensor array composed of a photoelectric conversion element and a switch TFT using non-single crystal silicon, e.g., amorphous silicon (hereinafter, abbreviated to a-Si); and a phosphor for converging the radiation to a visible light etc., in combination. Based on the above, the possibility that absolute digitalization thereof is realized with a large area is being increased.
The FPD can instantly read the radiation image and display the read image on a display in real time. Also, the image can be directly taken out as digital information, so that features of the FPD reside in easiness in storing data or handling the data inclusive of data processing and data transfer. It has been confirmed that various characteristics such as sensitivity are exhibited, although depending on photographing conditions, at a level equal to or more than that of a conventional S/F system or CR photographing method.
FIG. 10 is a schematic equivalent circuit diagram of the FPD. In the figure, reference numeral 101 denotes a photoelectric conversion element portion; 102, a switch TFT portion; 103, a switch TFT driving wiring; 104, a signal line; 105, a bias wiring; 106, a signal processing circuit; 107, a TFT driving circuit; and 108, an A/D converter unit.
The radiation such as X-ray enters from an upper portion on the paper and undergoes the conversion to the visible light through the phosphor (not shown). The conversion light is converted to charges by the photoelectric conversion element portion 101 and accumulated therein. After that, the TFT driving circuit 107 is used to operate the transfer TFT 102 through the TFT driving wiring to transfer the accumulated charges to the signal line 104. The charges thus transferred are processed by the signal processing circuit 106 and further subjected to A/D conversion in the A/D converter unit 108 before being outputted.
Basically, the above element structure is generally employed. In particular, regarding the photoelectric conversion element, various elements have been proposed including a PIN type photo diode (hereinafter, abbreviated to PIN type PD) or an MIS type Photo Detector (hereinafter, abbreviated to MIS type PD) adopted by the inventors of the present invention, for example.
FIG. 11 is a schematic plan view showing one pixel in a case where the MIS type PD is used for the photoelectric conversion element. In the figure, reference numeral 203 denotes a lower electrode of an MIS type PD portion; 202, a switch TFT driving wiring; 204, a gate electrode of the switch TFT; 208, a sensor bias wiring; 210, a signal line; 209, source/drain electrodes (hereinafter, abbreviated to SD electrodes) of the switch TFT; and 211, a contact hole.
Further, FIG. 12 is a schematic sectional view showing the elements that are schematically arranged in one pixel of FIG. 11. In the figure, reference numeral 201 denotes a glass substrate; 202, the switch TFT driving wiring; 203, the lower electrode of the MIS type PD; 204, the gate electrode of the switch TFT; 205, a gate insulating film; 206, an intrinsic a-Si film; 207, a hole blocking layer (n+ layer: ohmic contact layer); 208, the bias wiring; 209, the SD electrodes of the transfer TFT; 210, the signal line; 220, a protective film; 221, an organic resin layer; and 222, a phosphor layer.
Next, referring to FIGS. 13 to 17, a manufacturing method for the FPD using the conventional MIS type PD will be described. In the figures, the same reference numerals as in FIG. 11 are used.
As a first step thereof, on the glass substrate, the switch TFT driving wiring 202, the MIS type PD lower electrode 203, and the switch TFT gate electrode 204 are formed of a first metallic layer. FIG. 13 is a schematic plan view thereof.
As a second step thereof, the gate insulating film, the intrinsic a-Si film, the hole blocking layer (ohmic contact layer) are laminated in order.
As a third step thereof, the contact hole (connection hole) 211 is formed, through which the MIS type PD lower electrode 203 and the SD electrodes 209 of the switch TFT are connected. FIG. 14 is a schematic plan view thereof.
As a fourth step thereof, a second metallic layer is laminated thereon. After that, the bias wiring 208 is formed through first resist work. At this time, regions where the SD electrodes 209 of the switch TFT and the signal line 210 are formed as described below are left in an island-like shape. FIG. 15 is a schematic plan view thereof.
As a fifth step thereof, the SD electrodes 209 of the switch TFT and the signal line 210 are formed through second resist work. Following this, the n+ semiconductor layer is removed. Namely, a gap portion between the SD electrodes of the switch TFT is formed, while the n+ semiconductor layer in the MIS type PD portion is left as the electrode. FIG. 16 is a schematic plan view thereof.
As a sixth step thereof, isolation between the elements is performed. FIG. 17 is a schematic plan view thereof.
As a seventh step thereof, a protective layer is laminated thereon and portions unnecessary at the time of forming a wiring lead-out portion etc. are removed. Thereafter, the phosphor is bonded thereto using the organic resin or the like.
As apparent from FIGS. 11 and 12, since the MIS type PD and the switch TFT have the same layer structure, the FPD thus manufactured has an advantage in that high yield and low cost are realized with the simple manufacturing method. In addition, the FPD is evaluated to exhibit various characteristics such as the sensitivity, which are highly satisfactory. As a result, under the present circumstances, the above FPD is adopted as the apparatus used for the ordinary photographing instead of using the conventional S/F or CR method.
Further, as apparent from FIGS. 13 to 17, in the conventional case, 6 masks are used. That is, required are the masks for steps of (1) patterning the first metallic layer, (2) patterning the connection hole, (3) patterning the second metallic layer, (4) patterning the second metallic layer in the TFT portion/patterning the ohmic contact layer, (5) patterning for the element isolation, and (6) patterning the protective layer.
However, in the above FPD, the full-digitalization is attained with the large area. Eventually, the FPD is thus being employed mainly for the ordinary photographing. In terms of sensitivity, however, a further improvement is expected. Also, in order to achieve the fluorography, it is conceivable that the achievement of much higher sensitivity is indispensable.
FIG. 18 shows a 1-bit equivalent circuit of the FPD using the MIS type PD. In the figure, reference symbol C1 denotes a synthetic capacitance of the MIS type PD; C2, a parasitic capacitance formed on the signal line; Vs, a sensor bias potential; Vr, a sensor reset potential; SW1, a Vs/Vr changeover switch of the MIS type PD; SW2, an ON/OFF changeover switch of the transfer TFT; SW3, a signal line reset switch; and Vout, an output voltage.
The MIS type PD is applied with the potential Vs as the bias potential through the switch SW1 so as to turn the semiconductor layer into the depletion layer. In this state, the conversion light from the phosphor enters the semiconductor layer, positive charges blocked by the hole blocking layer are accumulated in the a-Si layer to cause a potential difference Vt. Subsequently, the switch SW2 is used to apply an ON voltage of the switch TFT to be outputted as the voltage Vout. The output Vout is read by a reading circuit (not shown), followed by resetting the signal line through the switch SW3. Thus, the outputs are sequentially read.
According to the above driving method, the switch TFT is turned ON on the line basis to thereby complete whole reading operation in one frame. After that, the MIS type PD is supplied with the reset potential Vr through the switch SW1 for reset and applied with the bias potential Vs again to start the accumulating operation for image reading.
A saturation value of the output Vout of the MIS type PD is approximately in proportion to the potential Vt. The potential Vt is defined by the product of Vs-Vr (bias voltage difference) and G (internal Gain). The internal Gain (G) is obtained as follows: Cins/(Cins+Csemi). The output voltage Vout is outputted substantially at a capacitance ratio of C1/C2 with respect to the potential Vt.
The sensitivity of the MIS type PD can be approximately represented by the above saturation output voltage in the light incidence state, i.e., a ratio of a signal component and the output voltage in a dark state, that is, a noise component.
The signal components generally depend on (1) a PD opening ratio, (2) a PD light incidence efficiency, in other words, a quantity of light incident on the intrinsic a-Si film, and further (3) the internal Gain.
On the other hand, it is confirmed that the noise components involve the various following factors: (1) shot noise: shot noise in proportion to the square root of the value of the sensor opening ratio; (2) KTC noise: KTC noise in proportion to the square root of the value of the C1 capacitance; (3) signal wiring noise: wiring noise in proportion to the value of the square root of the wiring resistance or C2 capacitance; (4) IC noise: IC noise in proportion to the C2 capacitance; and (5) gate wiring noise: wiring noise in proportion to the square root of the value of the wiring resistance.
In general, it is needless to say that either the increase in signal component or the reduction in noise component should be achieved, or both of them should be satisfied at the same time in order to increase the sensitivity. However, the signal components and the noise components are correlated. Thus, improvement of the former affects the latter. As a result, the improvement in sensitivity is not attained in many cases.
For example, in order to improve the signal components, in the case of increasing (1) the PD opening ratio as described above, it is conceivable that the wiring width or the space between the wirings is shrunk for the improvement. This would result in the increased noise components rather than the improvement because the wiring resistance or the parasitic capacitance of the signal line increases along with the miniaturization. That is, the signal components are improved, which undesirably involves the increase in noise component. Thus, in some cases, the sensitivity reduction is caused. Further, in association with the miniaturization, the wiring rule is made strict, so that the productivity may decrease, for example, the yield may be reduced.
Also, as for (2) the light incidence efficiency described above, similarly, the ohmic contact layer bonded to the a-Si film serving as the photoelectric conversion layer is needed to function as the upper electrode as well as the carrier blocking layer. Thus, it is necessary for the ohmic contact layer to have the thickness of about 50 nm or more, which involves the light absorption beyond the ignorable level. As a result, the light absorption in the n+ film leads to the reduction in sensitivity. Needless to say, when the n+ film is made thin, the resistance of the n+ film is conversely increased, with the result that the film cannot function as the PD upper electrode.
Also, in the case of increasing (3) the internal Gain described above, the a-Si film should be made thick or the gate SiN film should be made thin. However, the a-Si film is made thick while causing the reduction in transfer ability of the switch TFT, resulting in the increase in TFT size and the decrease in opening ratio. Also, as for the increase in the a-Si film thickness, in terms of the production problems concerning the stress thereof, the generation of the foreign matters, and the like, there is imposed the limitation. Also, as for the reduction in SiN film thickness, considering the dielectric voltage at the wiring intersections etc., there is similarly imposed the limitation. Assuming that the reduction in film thickness can be attained, the noise components are increased along with the increase in parasitic capacitance C2, which hardly leads to achievement of the considerable sensitivity improvement.
On the other hand, when focusing attention on the noise reduction, the gate wiring resistance is decreased. In this case, the gate wiring should have large film thickness or large width. However, the former leads to the decrease in dielectric voltage at the wiring intersections, while the latter leads to the decrease in opening ratio.
Also, when the wiring resistance of the signal line is decreased, the signal line should have the large film thickness or large width. However, the former involves not only the limitations in terms of production facilities due to the increased stress, but also the limitation on increase in film thickness from the viewpoint of working. Alternatively, the latter leads to the decrease in opening ratio similarly to the above case.
As explained above, with the existing structure, the sensitivity is optimized in design. In other words, for the realization of the much higher sensitivity, the improvement in basic structure, material, and manufacturing process is required.
On the contrary, various structures have been proposed, in which the opening ratio is increased by laminating the sensor elements on the switch elements. However, the switch elements and the sensor elements are formed on the different layers, resulting in the complicated process. Further, there arises a problem in that the number of masks increases as compared with the above case of forming the elements using the same layer.